Power-Aware ReRAM-Based Processing-in-Memory Architecture for Hyperdimensional Computing Using Clock Gating
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1SHEIK RIZWANA, 2GUTTULA VENKATARAMANA
Hyperdimensional Computing (HDC) is an emerging computing paradigm inspired by the human brain, where information is represented using high-dimensional vectors known as hyper vectors.
DOI:30.0485/ijearst.10.03.3493
1SHEIK RIZWANA, 2GUTTULA VENKATARAMANA
Hyperdimensional Computing (HDC) is an emerging computing paradigm inspired by the human brain, where information is represented using high-dimensional vectors known as hyper vectors.
DOI:30.0485/ijearst.10.03.3493
IoT-Enabled High Load Density Miniature Force Sensor System for Intelligent Robot Foot Probing and Obstacle Avoidance
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1Jampana Sushma 2Dr.R.V.V. Krishna
This project presents an enhanced version of a High Load Density Miniature Force Sensor for Probing with Robot Feet
DOI:30.0485/ijearst.10.03.3491
1Jampana Sushma 2Dr.R.V.V. Krishna
This project presents an enhanced version of a High Load Density Miniature Force Sensor for Probing with Robot Feet
DOI:30.0485/ijearst.10.03.3491
Power-efficient and Area-optimized Exposed Datapath Architecture Enhanced with a RISC-V Instruction Set
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1K. HEMANTH SURYA MANISAI, 2SATHIBABU MANDAPALLI
This project describes a 32-bit RISC microprocessor core that has been designed for portable applications.
DOI:30.0485/ijearst.10.01.3494
1K. HEMANTH SURYA MANISAI, 2SATHIBABU MANDAPALLI
This project describes a 32-bit RISC microprocessor core that has been designed for portable applications.
DOI:30.0485/ijearst.10.01.3494
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