IJEARST Volume 02, Issue 02, August 2026 Edition


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Power-Aware ReRAM-Based Processing-in-Memory Architecture for Hyperdimensional Computing Using Clock Gating []


Hyperdimensional Computing (HDC) is an emerging computing paradigm inspired by the human brain, where information is represented using high-dimensional vectors known as hyper vectors.

DOI:30.0485/ijearst.10.03.3493

IoT-Enabled High Load Density Miniature Force Sensor System for Intelligent Robot Foot Probing and Obstacle Avoidance []


This project presents an enhanced version of a High Load Density Miniature Force Sensor for Probing with Robot Feet

DOI:30.0485/ijearst.10.03.3491

Power-efficient and Area-optimized Exposed Datapath Architecture Enhanced with a RISC-V Instruction Set []


This project describes a 32-bit RISC microprocessor core that has been designed for portable applications.

DOI:30.0485/ijearst.10.01.3494

High-Speed Approximate Hybrid Floating-Point Multiplication Using Radix-16 Modified Booth Encoding for Butter fly unit []


This project presents floating-point operations and applies them to the implementation of Butterfly unit.

30.0485/ijearst.10.01.3495

Medical Waste Classification using Deep Learning and Convolutional Neural Networks (TensorFlow) []


This project focuses on developing an automated system for classifying medical waste using Deep Learning and Convolutional Neural Networks (CNNs).

30.0485/ijearst.10.01.3496

High-Performance ALU Architecture Using MGDI Based Logic Gates and Multiplexers []


This project presents the design of a low-power and area-efficient Arithmetic Logic Unit (ALU) using the Modified Gate Diffusion Input (MGDI) and Hybrid GDI design techniques.

30.0485/ijearst.10.01.3497

Power and Density optimized Architecture for 3D Semantic Segmentation with Offset-Wise Weight Quantization using Radix8 booth encoding []


Three-dimensional (3D) semantic segmentation plays a vital role in modern applications such as autonomous driving,

30.0485/ijearst.10.01.3500


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